Criticality Aware Latin Hypercube Sampling for Efficient Statistical Timing Analysis

Process variation is a major concern in the semiconductor industry today. Probabilistic statistical static timing analysis (SSTA), where random variables are used to represent arrival times, has been proposed as a method to address this challenge. However, there are a number of modeling and accuracy difficulties associated with probabilistic SSTA analysis and optimization methods, such as how to address the skew of arrival times efficiently and combined modeling of drivers and interconnect. In this paper we describe a method to improve the practicality of statistical static timing analysis (SSTA) by focusing on improving the efficiency of Monte Carlo based statistical timing analysis. We introduce a Criticality Aware Latin Hypercube Sampling (CALHS) approach to stratify the process variation space based on critical paths in the circuit and then intelligently sample. The result is that many fewer samples (up to 6.9X on the benchmark circuits studied) are needed to arrive at comparable accuracy in timing estimation compared to a random sampling approach. Also, in comparing a Monte Carlo-based SSTA to traditional SSTA approaches, we find over 50% less error in higher percentile delays for the largest circuits considered, using CALHS, even with a moderate number of samples.